This invention relates in general to semiconductor devices and in particular to semiconductor device structures which include an electrically isolated conductor which is adapted to receive electric charge from an electron beam.
State of the art developments in semiconductor devices and particularly in high density arrays of semiconductor devices in integrated circuits include numerous examples where stored charge is used to control device operation. One such example is the floating gate transistor described in U.S. Pat. No. 3,660,819, in which avalanche-injection is used to transfer charge to the electrically isolated gate of a field effect transistor. As disclosed in the patent, this semiconductor device structure provides the basis for an electrically alterable read-only-memory. Although this approach has proved useful, integrated circuit arrays of such semiconductor devices are inherently limited because of the spacing requirements associated with avalanche-injection.
Furthermore, during programming of the above device, avalanche-injection from the drain-substrate breakdown is used. The minimum channel length for a driver memory device of the above type is approximately 0.45 .mu.m for a -7.5 volt drain. For smaller channel lengths, a gate oxide breakdown will occur first. If the charging mechanism was other than avalanche-injection, the minimum channel length could be about 0.25 .mu.m for -2.0 volt drain voltage, or even smaller for lower drain voltages. Also, during programming, the X and Y decoder devices in a memory, as above, operate at the programming voltages, e.g. -7.5 volts. At this voltage, the minimum channel length is determined, as above, by drain-substrate breakdown.
To store a maximum charge of 4.times.10.sup.12 electrons/cm.sup.2 during avalanche-injection a gate charging current of about 10.sup.-7 amp/cm.sup.2 is necessary for about 100 to 5000.mu. seconds.
In extremely dense arrays of transistors or other semiconductor device structures, the use of avalanche-injection to create floating gates is not possible because the high voltages required for avalanche-injection cause voltage breakdown between adjacent device regions.
Additionally, with prior art devices as set forth above, only p-channel devices can be programmed without extensive modifications and/or extremely slow programming times.
The avalanche-injection technique stores a limited charge on the floating gate, because the charge injected to the gate alters the surface doping. Eventually, the drain-substrate breakdown is inhibited and the injection stops.
Another developing technology which relates to high density integrated circuit structures is electron beam technology. The advent of computer controlled systems for rapidly positioning electron beams which have extremely small dimensions have made it possible to fabricate very small semiconductor devices. Dimensionally, electron beam fabrication systems can resolve lines and spaces as small as one-half micron. These computer controlled electron beam systems are also adapted for automatic registration so that the system can automatically locate and register on a particular location on a semiconductor wafer. A registration capability of this type makes it possible to preselect any particular region on any particular integrated circuit "chip" on a given semiconductor wafer. Additional details on computer controlled electron beam fabrication systems can be obtained by referring to the Technical Digest of the 1976 International Electron Devices Meeting, Session 18: "Device Technology-Electron Beam Technology and Applications," pps. 431-449.
Electron beams have also been proposed in various schemes for information storage including electrostatic storage on insulators, thermoplastic recording and electron beam exposure of photographic emulsions. One such scheme calls for applying a positive bias voltage to the metal gate of an insulated gate field effect transistor (IGFET) and then bombarding the gate with an electron beam. As a result of the bombardment, a positive charge accummulates in the gate oxide of the IGFET near the semiconductor oxide interface. The charge thus stored controls the conductive state of the IGFET and thereby provides the basis for an IGFET memory circuit. A complete discussion of this type IGFET memory is provided in the Proceedings of the IEEE, Volume 56, No. 2, February 1968, An Electron Beam Activated Switch and Associated Memory, page 158, McDonald and Eberhart. A particular constraint of this approach is that the electron beam voltage must be large enough to ensure complete penetration of the metal gate electrode of the IGFET and the associated oxide layer and the bombardment charge density must be sufficient to charge the oxide to saturation.